Abstract

As hardware security threats continue to evolve, ensuring the integrity of integrated circuits (ICs) has
become critical. One such emerging threat is the insertion of hardware Trojans malicious modifications to an
IC’s design that remains undetected during traditional verification processes. These Trojans can compromise
the system’s functionality or leak sensitive information, posing significant risks in sensitive applications such
as military, automotive, and medical devices. To address this issue, this paper proposes a novel approach
based on compressive sensing (CS) for Trojan triggering and detection during the pre-silicon phase of
hardware development. The proposed technique leverages the sparse nature of hardware Trojan behavior
and applies CS to efficiently capture and reconstruct Trojan-induced anomalies in a circuit’s response.
Compressive sensing enables the detection of subtle deviations from expected normal behavior using fewer
measurements than traditional methods, thereby reducing the overhead in terms of computational resources
and time. The approach involves designing a triggering mechanism that exploits the sparse characteristics of
Trojans, coupled with a detection algorithm that reconstructs possible Trojan patterns from compressed
sensor data. We validate the effectiveness of this approach using simulation-based experiments,
demonstrating that the CS-based method can identify Trojans with high accuracy and minimal false positives.
Additionally, we discuss the pre-silicon advantages of this method, highlighting its ability to detect Trojans
early in the design phase, before actual hardware fabrication. The proposed solution not only enhances the
reliability of hardware security but also provides a scalable approach to safeguarding against increasingly
sophisticated threats in next-generation IC designs. This work contributes to the growing field of hardware
security by introducing a proactive, efficient, and scalable Trojan detection methodology, offering a
significant step towards reliable pre-silicon validation for secure hardware systems.